Chuan-Jane Chao

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The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then(More)
Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our(More)
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45 /spl mu/m-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with(More)
ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/ O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake(More)
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are(More)
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