Chu Shik Jhon

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| The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called cross-talk(More)
The manufacturing process of microprocessors becomes increasingly fine and the clock frequency is rapidly growing. Since the corresponding power consumption, however, is not reduced, power density is increased dramatically. The generated heat by the power density induces high temperature. The high temperature causes many problems: calculation errors, aging,(More)
Cache compression has been studied to increase the effective cache size by storing the cache blocks in a compressed form in the cache. However, it also generates additional write operations during the compressing and compacting of cache blocks. Since increasing the write operations leads to a surging of dynamic energy consumption and a shortening of the(More)
As technology scales down, leakage energy accounts for a greater proportion of total energy. Applying the drowsy technique to a cache, is regarded as one of the most efficient techniques for reducing leakage energy. However, it increases the Soft Error Rate (SER), thus, many researchers doubt the reliability of the drowsy technique. In this paper, we show(More)
The Bulk Synchronous Parallel (BSP) model of computation [9] was first proposed by Valiant as a bridging model between hardware and software for general-purpose parallel computation. The main objective of the model is to provide an abstract machine which allows the design of parallel programs that can be executed efficiently on a variety of architectures. A(More)