Chrystian Guth

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Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discreteness of the problem, along with complex timing models, stringent constraints and ever increasing circuit sizes make the problem very difficult to tackle. Lagrangian Relaxation is an effective(More)
Timing-driven placement (TDP) finds new legal locations for standard cells so as to minimize timing violations while preserving placement quality. Although violations may arise from unmet setup or hold constraints, most TDP approaches ignore the latter. Besides, most techniques focus on reducing the worst negative slack and let the improvements on total(More)
Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR)(More)
During physical synthesis, global placement and incremental optimization steps such as gate sizing, buffer insertion and timing-driven placement, produce placements where cells are overlapped or misaligned with respect to sites and rows predefined in the used standard cell library. Therefore, a legalization procedure must be used to keep the placement(More)
The increasing impact of interconnections on overall circuit performance makes timing-driven placement (TDP) a crucial step toward timing closure. Current TDP techniques improve critical paths but overlook the impact of register placement on clock tree quality. On the other hand, register placement techniques found in the literature mainly focus on power(More)
Circuit legalization removes overlaps and keeps cell alignment with power rails while minimizing total cell displacement. Legalization is applied not only after global placement, but also after incremental optimization steps like detailed placement, gate sizing, and buffer insertion. Applying full legalization after such incremental optimizations is too(More)
The increasing impact of interconnections on the overall circuit performance renders physical design a crucial step to timing closure. Several techniques are used to optimize timing within the flow, such as gate sizing, buffer insertion, and timing-driven placement (TDP). Unfortunately, gate sizing and buffer insertion are not capable of modifying the(More)
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