Christopher YAP

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Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show(More)
Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ fault detection technique for wafer warpage in lithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling,(More)
Scan diagnosis based fault isolation technique using Electronic Design Automation (EDA) software tool is highly effective and commonly adopted for product chain and logic yield learning. For every new device introduction, prior to implementation of scan diagnosis for yield ramp, it is necessary to validate the success and accuracy of the test patterns(More)
Conventional software scan diagnosis using Electronic Design Automation (EDA) tools and hardware diagnosis using frequency mapping technique, are established methodologies for broken scan chains fault isolation. This work proposes a diagnostic workflow that integrates both methodologies to enhance accuracy and reduce turnaround time for debug. Experimental(More)
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