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Single-event upsets from particle strikes have become akey challenge in microprocessor design. Techniques todeal with these transient faults exist, but come at a cost.Designers clearly require accurate estimates of processorerror rates to make appropriate cost/reliability trade-offs.This paper describes a method for generating theseestimates.A key aspect of(More)
<i>The growth of the Internet as a vehicle for secure communication and electronic commerce has brought cryptographic processing performance to the forefront of high throughput system design. This trend will be further underscored with the widespread adoption of secure protocols such as secure IP (IPSEC) and virtual private networks (VPNs).</i> <i>In this(More)
We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with(More)
The use of simulation is well established in academic and industry research as a means of evaluating architecture trade-offs. The large code base, complex architectural models, and numerous configurations of these simulators can consternate those just learning computer architecture. Even those experienced with computer architecture, may have trouble(More)
Dynamic binary translation (DBT) has been widely used as a means to run applications created for one instruction-set architecture (ISA) on top of processors with a different ISA. Given the great amount of legacy software developed for PCs, based on the Intel&#174; Architecture (IA) ISA, a lot of attention has been given to translating IA to other ISAs. The(More)