Christopher Mineo

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AN INCREASING NUMBER of integrated solutions involve the stacking of chips to reduce system size. You can find wire-bonded stacks of processors and memories in cell phones, PDAs, and flash cards. But is physical size of the system the only benefit of stacking chips? Does this minia-turization provide potential performance benefits? Until recently, practical(More)
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing(More)
—This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18µm MIT Lincoln Laboratories 3D FDSOI 1.5V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm 2 per tier was designed and tested. It is the first of its kind to demonstrate successful inter-tier signaling in a complex three dimensional(More)
3D-ICs promise to reduce wire-delays, but non-idealities threaten to diminish the benefit. This paper presents an analysis of the performance improvement of a standard-cell implementation of an FFT when designed for the three-tier process from MIT Lincoln Labs. The methodology is presented, along with analyses of delay, routing congestion, and heat. The(More)
Contention of communications across a switched network that connects multiple compute nodes in a distributed-memory cluster may seriously degrade performance of parallel code. The InfiniBand network is the most popular interconnect for compute clusters. While one may correctly assume that increased resource contention leads to decreased application(More)
Stochastic estimates of wire-length based on Rent's rule predict a benefit of 3D integration over traditional ICs, tapering off with a 50% reduction for 8 tiers. However, Rent's rule is unnecessarily pessimistic, because it assumes an extrapolation of architectures that were conceived in two dimensions. This paper examines the gains possible in several 3D(More)
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