Christopher D. LeBlanc

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A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. The feedback through the charge pumps(More)
This paper presents a new spread spectrum clock generator (SSCG) circuit for EMI reduction. The proposed design adopts a standard integer-N phased locked loop (PLL) with two dual-voltage-controlled oscillators (VCOs). A frequency modulation loop is implemented with a digital frequency limit detector to direct the spectrum-spreading profile. An integrator is(More)
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