• Publications
  • Influence
Procedure placement using temporal-ordering information: dealing with code size expansion
TLDR
In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Expand
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Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency
TLDR
We propose a new approach based on coalescing and a precise view of interferences, in which correctness and optimizations are separated. Expand
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Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How
TLDR
This work was supported by a contract with STMicroelectronics, Grenoble, France. Expand
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Register allocation and spill complexity under SSA
TLDR
This report deals with the problem of choosing which variables to spill during the register allocation phase, which is a highly studied problem for compiler design, but nevertheless NP-complete. Expand
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Dynamic Elimination of Overflow Tests in a Trace Compiler
TLDR
We provide an analysis that removes unnecessary overflow tests from TraceMonkey, the JavaScript engine in the Mozilla Firefox browser. Expand
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Optimizing translation out of SSA using renaming constraints
TLDR
We propose a method to reduce the /spl Phi/-related copies during the out of SSA translation, thanks to a pinning-based coalescing algorithm that is aware of renaming constraints. Expand
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Code generator optimizations for the ST120 DSP-MCU core
TLDR
The ST120 Digital Signal Processor Micro-Controller Unit (DSP–MCU) core was designed by STMicroelectronics in order to meet the ever-increasing digital signal processing requirements of portable and consumer applications. Expand
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Collective Mind, Part II: Towards Performance- and Cost-Aware Software Engineering as a Natural Science
TLDR
We present our practical and collaborative solution to this problem via light-weight wrappers around any software piece when more than one implementation or optimization choice available. Expand
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Data-flow/dependence profiling for structured transformations
TLDR
We develop poly-prof, an end-to-end infrastructure for dynamic binary analysis, which produces feedback about the potential to apply complex program rescheduling. Expand
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Compilation and virtualization in the HiPEAC vision
TLDR
This paper describes the HiPEAC vision of embedded virtualization as it has developed during two years of discussion among the members of the cluster on binary translation and virtualization. Expand
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