- Full text PDF available (4)
- This year (0)
- Last five years (0)
Accelerating discrete event simulation can be achieved by using parallel architectures. The use of dedicated hardware is a possible alternative in some special domains like logic simulation. However, few studies have focused on general cases. This paper presents an innovative solution using a recent hardware technology called FPGA (<italic>Field… (More)
In the wide eld of parallel architectures, machines involving fpgas on each node have appeared during the last years. Connecting these reconngurable components opens new research horizons. Expensive control tasks required by distributed applications may then be accelerated using application speciic hard-wired elements. A derivation from a standard algorithm… (More)
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional description of the circuit, with no timing consideration. On the other hand, simulation runs mainly on subsets of the entire input domain. Furthermore, these tools provide results… (More)
Accelerating discrete event simulation can be achieved in two principal ways : either by using dedicated coproces-sors in order to speed up event evaluation or control task execution (such as enqueue/dequeue) and/or by developing or improving algorithms and protocols which take benefit of today's widely used general purpose parallel computers. In this… (More)
Go beyond the bells and whistles to learn how to select this important assessment tool.