Christoph Scheurich

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In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access latency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss. Write buffers are often included in a pipelined machine to(More)
M ultiprocessors, especially those constructed of relatively low-cost microprocessors , offer a cost-effective solution to the continually increasing need for computing power and speed. These systems can be designed either to maximize the through-put of many jobs or to speed up the execution of a single job; they are respectively called throughput-oriented(More)
This paper shows that cache coherence protocols can implement indivisible synchronization primitives reliably and can also enforce sequential consistency. Sequential consistency provides a commonly accepted model of behavior of multiprocessors. We derive a simple set of conditions needed to enforce sequential consistency in multiprocessors. These conditions(More)
High-performance multiprocessors must incorporate a high-bandwidth, short-latency memory aggregate to support maximal processor utilization. Cache memories are often used to meet this requirement. The performance of cache-based, shared-memory multiprocessors can suffer greatly from moderate cache miss rates because of the usually high ratio between(More)
t the time when the research work for the above paper was done, Michel Dubois was a starting assistant professor and Christoph Scheurich was a Ph.D. student at the University of Southern California. In this retrospective they both relate their experience on the work they did jointly more than 10 years ago. The problems of coherence and consistency have been(More)
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