Christina C.-H. Liao

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Power cost and wire cost are two most critical issues in scan-chain optimization for modern VLSI testing. Many previous works used layout-based partitioning and greedy heuristics to synthesize multiple scan chains, making themselves suffer from (1) cost-metric monotonicity and (2) crossing-edge problem. Therefore, in this paper, we propose cost-driven(More)
This brief addresses the problem of scan-chain ordering under a limited number of through-silicon vias (TSVs), and proposes a fast two-stage algorithm to compute a final order of scan flip-flops. To enable 3-D optimization, a greedy algorithm, multiple fragment heuristic, is modified and combined with a dynamic closest-pair data structure, FastPair, to(More)
We demonstrate three-dimensional (3-D) self-aligned [IrO2–IrO2–Hf]–LaAlO3–Ge-on-Insulator (GOI) CMOSFETs above 0.18m Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2–LaAlO3–GOI p-MOSFETs and IrO2–Hf–LaAlO3–GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm Vs respectively, without depredating the(More)
The unwanted high threshold voltage (Vt) is the major challenge for metal-gate/high-j CMOS especially at small equivalent-oxide-thickness (EOT). We have investigated the high Vt issue that is due to flat-band voltage (Vfb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the Vfb roll-off(More)
The scaling limit for VLSI gate oxide (SiO 2 ) is 15}20 As that is determined by the large direct-tunneling leakage current. Further scaling to improve device performance can be obtained using a higher dielectric constant material. We have studied the Al 2 O 3 to use as an alternative gate dielectric. To ensure good quality, Al 2 O 3 is thermally oxidized(More)
In this paper, a novel microstrip-line layout is used to make accurate measurements of the minimum noise figure (NFmin) of RF MOSFETs. A low NFmin of 1.05 dB at 10 GHz was directly measured for 16-finger 0.18-μm MOSFETs, without de-embedding. Using an analytical expression for NFmin, we have developed a self-consistent dc current–voltage, S-parameter, and(More)
The shallow trap energy in SONOS Charge-Trapping Flash (CTF) is the fundamental challenge for required good retention, especially at elevated temperatures. Although the high temperature retention can be improved by BE-SONOS, this is traded off the slow erase speed. To address these issues, we have fabricated a new Charge-Trapping-Engineered Flash (CTEF)(More)
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