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This paper examines the characteristics of 6T SRAM Cell Data Retention Voltage (DRV). It also presents different DRV minimization techniques for ULP applications. The 6T SRAM cell is designed in 180nm CMOS technology. The cell is simulated to by varying different DRV dependent parameters to understand the effects on it.
This paper examines the factors that affect the Static Noise Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while varying several parameters that affect SRAM operations. These parameters are temperature, threshold voltage, supply voltage, cell… (More)