Christian Venerus

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Fractionalphase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps ( -PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase(More)
This paper presents the first published fully-integrated digital fractionalPLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL’s quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL ( -PLL). Hence, the quantization noise is highpass shaped(More)
Fractionalphase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps ( -PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase(More)
Fractional- N phase-locked loops (PLLs) typically use noise-shaping coarse quantizers to control their instantaneous output frequency. The resulting quantization noise and its running sum inevitably get distorted by non-ideal analog components within the PLL, which induces undesirable spurious tones in the PLL's output signal. A recently proposed quantizer,(More)
Fractional-N phase-locked loop frequency synthesizers based on time-todigital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps (ΔΣ-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their(More)
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