• Publications
  • Influence
A Survey and Evaluation of FPGA High-Level Synthesis Tools
  • R. Nane, V. Sima, +9 authors K. Bertels
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of…
  • 1 October 2016
TLDR
High-level synthesis (HLS) is increasingly popular for the design of high performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. Expand
  • 254
  • 21
  • PDF
Bambu: A modular framework for the high level synthesis of memory-intensive applications
TLDR
This paper presents bambu, a modular framework for research on high-level synthesis currently under development at Politecnico di Milano. Expand
  • 74
  • 8
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems
TLDR
We propose an ant colony optimization heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. Expand
  • 126
  • 6
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An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems
TLDR
We present an FPGA-based infrastructure that facilitates cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. Expand
  • 24
  • 3
  • PDF
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
TLDR
This paper presents a methodology for design space exploration (DSE) in high-level synthesis (HLS), based on a multi-objective genetic algorithm. Expand
  • 32
  • 2
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HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms
TLDR
The hArtes toolchain provides the option of automatic or semi-automatic support for this mapping for heterogeneous multicore platforms. Expand
  • 29
  • 2
  • PDF
HW/SW methodologies for synchronization in FPGA multiprocessors
TLDR
We introduce two hardware synchronization modules for Xilinx MicroBlaze systems, with local polling or queuing mechanisms for locks and barriers, and present a comparison of these solutions to alternative designs. Expand
  • 20
  • 2
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A runtime adaptive controller for supporting hardware components with variable latency
TLDR
In this paper, we present an innovative lightweight controller architecture able to automatically adjust its behavior at run-time. Expand
  • 17
  • 2
TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis
TLDR
We propose TAO as a comprehensive solution based on high-level synthesis to raise the abstraction level and apply algorithmic obfuscation automatically. Expand
  • 11
  • 2
Automatic run-time manager generation for reconfigurable MPSoC architectures
TLDR
This paper presents a flow that allows to automate the generation of the RTM for a reconfigurable MPSoC on a FPGA target device. Expand
  • 9
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