Chris Schläger

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We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with other hardware and software components. A common approach to the modeling of processors for HW/SW co-verification relies on instruction-accurate ISA models combined (i.e. wrapped) with(More)
Summary form only given. This presentation will discuss the challenges of modern PC systems to reduce their power consumption. While efforts are made on all levels from the silicon to the software PC systems still use 2 to 3 orders of magnitude more power than mobile devices. The presentation will outline some of the reasons for this and how this problem is(More)
High complexity and development costs of processorbased DSP and embedded designs permanently force the hardware and software designers to develop and intensively use processor abstractions in form of abstract processor models for specification, design, and verification of processor hardware and software. Based on the SuperSim processor modeling technology(More)
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