Chris N. Hinds

Learn More
This paper presents the detailed design of the ARM VFP11 divide and square root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit recurrence algorithm, and this paper describes a novel acceleration technique employed to achieve the required processor clock frequency of up to 750 MHz in 90 nm CMOS. Logical(More)
  • 1