Chris Litteken

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A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has(More)
Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The(More)
This paper addresses several key aspects of integrated reliability for the Intel 45nm logic technology with high-K metal gate (HK+MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor,(More)
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