Chris J. Myers

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Specification for circuit usually trys to accomplish certain goals. Examples: Protocol never deadlocks. Whenever there is a request, it is followed by an acknowledgement possibly in a bounded amount of time. Can check by simulating a number of important cases. Simulation does not guarantee correctness of the design. Big problem in asynchronous design where(More)
In this paper we present a systematic procedure to synthesize timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asyn-chronous circuits. In addition, our timed circuits also tend to be more eecient, in both speed and area, compared with traditional(More)
This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed(More)
This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard-freedom. First, we present boolean covering conditions that guarantee the standard C-implementations(More)
The re-use of previously validated designs is critical to the evolution of synthetic biology from a research discipline to an engineering practice. Here we describe the Synthetic Biology Open Language (SBOL), a proposed data standard for exchanging designs within the synthetic biology community. SBOL represents synthetic biology designs in a(More)
This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state space by considering partially ordered sets of events rather than linear sequences. This approach avoids the explosion of timed states typical of highly concurrent systems by(More)
In order to efficiently analyze the complicated regulatory systems often encountered in biological settings, abstraction is essential. This paper presents an automated abstraction methodology that systematically reduces the small-scale complexity found in genetic regulatory network models, while broadly preserving the large-scale system behavior. Our method(More)
Models of cyber-physical systems are inherently complex since they must represent hardware, software, and the physical environment. Formal verification of these models is often precluded by state explosion. Fortunately, many important properties may only depend upon a relatively small portion of the system being accurately modeled. This paper presents an(More)
This dissertation addresses the problem of formally verifying the orre tness of pipelined mi ropro essors at the mi ro-ar hite tural level of abstra tion. Contemporary pro essor designs are highly omplex, employing sophisti ated performan e enhan ing te hniques su h as supers alar pipelining, out-of-order exe ution, bran h predi tion and spe ulative exe(More)
Embedded systems are composed of a heterogeneous collection of digital, analog, and mixed-signal hardware components. This paper presents a method for the verification of systems composed of such a variety of components. This method utilizes a new model, timed hybrid Petri nets (THPN), to model these circuits. In particular, this paper describes an(More)