Chris Conger

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Before any application is migrated to a reconfigurable computer (RC), it is important to consider its amenability to the hardware paradigm. In order to maximize the probability of success for an application's migration to an FPGA, one must quickly and with a reasonable degree of accuracy analyze not only the performance of the system but also the required(More)
RapidIO is an emerging standard for switched interconnection of processors and boards in embedded systems. We use discrete-event simulation to evaluate and prototype RapidIO-based systems with respect to their performance in an environment targeted towards space-based radar applications. This application class makes an ideal test case for a RapidIO(More)
Space-based radar is a suite of applications that presents many unique system design challenges. In this paper, we investigate use of RapidIO, a new high-performance embedded systems interconnect, in addressing issues associated with the high network bandwidth requirements of real-time ground moving target indicator (GMTI), and synthetic aperture Radar(More)
The design of space systems capable of performing realtime Synthetic Aperture Radar (SAR) is a significant challenge in HPEC due to the high processor, memory, and network requirements imposed by SAR. However, building a system to support SAR and other Space-Based Radar (SBR) algorithms simultaneously is an even greater challenge. This presentation(More)
Space-Based Radar (SBR) processing is a processorand communication-intensive HPEC application that presents unique design challenges. This talk will concentrate on the presentation of simulation results of mapping a parallel Ground Moving Target Indicator (GMTI) application on an embedded multiprocessor satellite processing system featuring a RapidIO(More)
In this article, we study optimization of a RapidIO network and FPGA-based computation engines to address the taxing requirements of a set of real-time Ground-Moving Target Indicators (GMTI) and Synthetic Aperture Radar (SAR) kernels for Space-Based Radar (SBR). By employing a RapidIO hardware testbed and validated simulation, we determine key trade-offs in(More)
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increased functionality. Even though recent advances in Xilinx’s Virtex-4 and Virtex-5 FPGA devices and design tools significantly improve the practicality of incorporating PR,(More)
Recent advances in Xilinx’s FPGA devices and design tools significantly improve the practicality of incorporating dynamic partial reconfiguration into high-performance embedded computing systems. By taking advantage of internal configuration access ports, Xilinx FPGAs are capable of in-situ partial reconfiguration without the need for external components, a(More)