Chris Conger

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Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increased functionality. Even though recent advances in Xilinx's Virtex-4 and Virtex-5 FPGA devices and design tools significantly improve the practicality of incorporating PR,(More)
Before any application is migrated to a reconfigurable computer (RC), it is important to consider its amenability to the hardware paradigm. In order to maximize the probability of success for an application's migration to an FPGA, one must quickly and with a reasonable degree of accuracy analyze not only the performance of the system but also the required(More)
The design of space systems capable of performing real-time Synthetic Aperture Radar (SAR) is a significant challenge in HPEC due to the high processor, memory, and network requirements imposed by SAR. However, building a system to support SAR and other Space-Based Radar (SBR) algorithms simultaneously is an even greater challenge. This presentation(More)
Space-Based Radar (SBR) processing is a processor-and communication-intensive HPEC application that presents unique design challenges. This talk will concentrate on the presentation of simulation results of mapping a parallel Ground Moving Target Indicator (GMTI) application on an embedded multiprocessor satellite processing system featuring a RapidIO(More)
Space-based radar is a suite of applications that presents many unique system design challenges. In this paper, we investigate use of RapidIO, a new high-performance embedded systems interconnect, in addressing issues associated with the high network bandwidth requirements of real-time ground moving target indicator (GMTI), and synthetic aperture Radar(More)
Space-based radar applications continue to receive increasing interest from the research community, and new technologies are emerging that will help to make the vision of real-time, on-board, high-volume data processing a reality for next-generation space platforms. Isolated kernel benchmarks may not accurately capture true system performance in the context(More)
In this article, we study optimization of a RapidIO network and FPGA-based computation engines to address the taxing requirements of a set of real-time Ground-Moving Target Indicators (GMTI) and Synthetic Aperture Radar (SAR) kernels for Space-Based Radar (SBR). By employing a RapidIO hardware testbed and validated simulation, we determine key trade-offs in(More)
Increasingly powerful radiation-hardened FPGAs, ASICs, and conventional processors along with high-performance embedded interconnect technologies are helping to enable the on-board processing of real-time, high-resolution radar data on satellites and other space platforms. The streaming nature of most Space-Based Radar (SBR) algorithms calls for(More)
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