Chr. Werner

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This paper presents simulation results for crosstalk noise in future CMOS generations down to 35 nm features. The noise oltage is calculated from circuit simulations with lumped RLC networks and static CMOS cells. A static noise margin is derived from inverter characteristics of NAND and NOR gates and a critical wire length is calculated from considering(More)
Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23ps but its aperture center is more sensitive to supply(More)
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