Chouki Aktouf

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The article proposes an approach that divides testing into three phases: router testing, RAM block testing, and distributed processor testing. This test strategy was implemented for the on-chip multiprocessor architecture of a fine-grain, massively parallel machine developed in 1995 at the National Polytechnic Institute of Grenoble. The hierarchical(More)
This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (DFT) architectures and network management protocols to take full benefits from existing networking infrastructures. By running intensive experimentation on ITC'99 and ITC'02 design(More)
This paper shows how to adapt the P1500 Design-For-Test standard through network management protocols to make the testing problem of System-On-Chips (SoCs) easier and cost-effective. For this purpose, a SoC is analyzed as a distributed system in which its own basic components or IP Cores (Intellectual Proprieties) are considered as network agents according(More)
While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability(More)
Competent design of hierarchical interfaces for hardware/software systems needs the convergence of three concurrent research directions: the study of hierarchy types, the intelligent communication between different domains, the formalization of verification/test. We aim to extend the theory of hierarchy types, in order to integrate communication properties(More)