Choongyeun Cho

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Realization of millimeter-wave (MMW) communication data link has been explored through VCO designs in CMOS technology [1-9]. While a higher VCO oscillation frequency has been pursued by driving VCO designs up to the technology limits, their manufacturability has been a concern. Due to increasing process variation in sub-100nm technologies, the VCO designs(More)
As an essential clock-system component, millimeter-wave dividers have been implemented for Vand W-band channels [1-8]. This has also served as a standard benchmark vehicle that reveals highspeed and low-power performances of a technology. Through technol ogy scaling, CMOS CML static divider high-frequency performances have been scaled [6-8], and they are(More)
A 2:1 static frequency divider using a bandpass load was fabricated in a digital 90 nm SOI CMOS technology. The divider exhibits a maximum operating frequency of 81 GHz at 1.2 V, and a core power of 15.6 mW. The divider can operate down to 0.5 V at a maximum operating frequency of 75.6 GHz with a core power of 2.75 mW.
A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the(More)
A frequency divider is an essential and critical building block in high-performance clock synthesizers. Since the frequency divider operates at the highest frequency in the system in order to prescale the high-frequency VCO output, the divider speed and power trade-off should be carefully considered at an early design stage. In particular, above 50GHz, the(More)
A mixed-signal circuit's performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process(More)
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data-driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates(More)
Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep submicron technology. However, it is difficult to accurately model systematic process variability due to the complicated and interrelated nature of physical mechanisms of variation. In this paper, a simple and practical method is(More)
This paper reports a new strip-patterned integrated inductor that actively engages metal filling rules leading to reduced manufacturing cost and process-induced uncertainties while simultaneously maintaining state-of-the-art performance. The strip-patterned inductor consists of parallel horse shoe-shape metal lines in the foot print of a single-line(More)