Choongyeun Cho

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Realization of millimeter-wave (MMW) communication data link has been explored through VCO designs in CMOS technology [1-9]. While a higher VCO oscillation frequency has been pursued by driving VCO designs up to the technology limits, their manufac-turability has been a concern. Due to increasing process variation in sub-100nm technologies, the VCO designs(More)
As an essential clock-system component, millimeter-wave dividers have been implemented for V-and W-band channels [1-8]. This has also served as a standard benchmark vehicle that reveals high-speed and low-power performances of a technology. Through technol ogy scaling, CMOS CML static divider high-frequency performances have been scaled [6-8], and they are(More)
A frequency divider is an essential and critical building block in high-performance clock synthesizers. Since the frequency divider operates at the highest frequency in the system in order to pre-scale the high-frequency VCO output, the divider speed and power trade-off should be carefully considered at an early design stage. In particular, above 50GHz, the(More)
CMOS VCOs have been implemented for mm-wave applications [1-7], however , as the required channel bandwidth for these applications increases, wide-range VCO tuning is becoming more challenging. Even without taking into account the process variability in nanometer CMOS, a single VCO hardly achieves requirements for a mm-wave band and phase-noise performance,(More)
– A mixed-signal circuit's performance and yield dependency on process variation are investigated with numerical circuit solution, statistical simulation, and implemented circuit measurement in 65nm partially-depleted silicon-on-insulator CMOS process. Increased relative variation in 65nm process is examined with site-to-site and wafer-to-wafer process(More)
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical data-driven approach identifies device characteristics that are most correlated with a product performance, and estimates performance yield. A statistical method that isolates(More)
— This paper reports a new strip-patterned integrated inductor that actively engages metal filling rules leading to reduced manufacturing cost and process-induced uncertainties while simultaneously maintaining state-of-the-art performance. The strip-patterned inductor consists of parallel horse shoe-shape metal lines in the foot print of a single-line(More)
—This paper presents a practical method to estimate IC product performance and parametric yield solely from a well-chosen set of existing electrical measurements intended for technology monitoring at an early stage of manufacturing. We demonstrate that the components of mmWave PLL and product-like logic performance in a 65nm SOI CMOS technology are(More)
This paper presents a simple yet effective method to analyze process variations using statistics on manufacturing in-line data without assuming any explicit underlying model for process variations. Our method is based on a variant of principal component analysis and is able to reveal systematic variation patterns existing on a die-to-die and wafer-to-wafer(More)