Chong-liang Ooi

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With faster CPU clocks and wider pipelines, all relevantmicroarchitecture components should scale accordingly.There have been many proposals for scaling the issue queue,register file, and cache hierarchy. However, nothing has beendone for scaling the load/store queue, despite the increasingpressure on the load/store queue in terms of capacity andsearch(More)
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., implicit threads) from the sequential execution stream and speculatively executes them in parallel on multiple processor cores. These proposals augment a conventional multiprocessor,(More)
Recent proposals for multithreaded architectures allow threads with unknown dependences to execute speculatively in parallel. These architectures use hardware <italic>speculative storage</italic> to buffer uncertain data, track data dependences and roll back incorrect executions. Because <italic>all</italic> memory references access the speculative storage,(More)
Recent proposals for multithreaded architectures employ speculative execution to allow threads with unknown dependences to execute speculatively in parallel. The architectures use hardware speculative storage to buffer speculative data, track data dependences and correct incorrect executions through roll-backs. Because <i>all</i> memory references access(More)
In this paper, the authors mention that there are two forms of TLP for Chip multiprocessors (CMPs): explicit threading and implicit threading. However, explicit threading is hard to program manually and, if automated, is limited in performance due to serialization of unanalyzable program segments. Implicit threading, on the other hand, requires buffering of(More)
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