Chirn Chye Boon

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However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and(More)
Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band application, the requirements of PLLs keep getting higher. In an mm-wave direct-conversion transceiver, the quadrature LO signals generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method(More)
This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series(More)
Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Abstract—A receiver front end(More)
Title Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from(More)
—A fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) is proposed. Through a particular symmetrical coupling network formed by diode-connected transistors, the in-phase coupling is realized in the IPIC-QVCO, which reduces both phase noise and phase error. A compact(More)
Since the phase-locked loop (PLL) circuit was proposed in the 1930s, it is being used for a lot of situations when precise revolution produced high speed integrated service networks even software PLLs are now used in engineering applications (16) A. given in a handbook on synchronization and communications " We to the understanding and applications of phase(More)
However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and(More)
This book provides the most comprehensive and in-depth coverage of the latest circuit design developments in RF CMOS technology. It is a practical and cutting-edge guide, packed with proven circuit techniques and innovative design methodologies for solving challenging problems associated with RF integrated circuits and systems. This invaluable resource(More)