Chingwei Yeh

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Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the(More)
Circuit clustering plays a fundamental role in hierarchical designs. identifying strongly connected components in the circuits can significantly reduce the complexity of the design and improve the performance of the design process. However, there hm not been a clear objective function for circuit clustering. In this paper, we present a new clustering metric(More)
Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous researches focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this paper, we present the layout techniques that(More)
This paper proposes a flexible hardware solution and the associated energy-aware IP core design for computing the variable-length discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) required in the MPEG4 shape-adaptive DCT/IDCT (SA-DCT/IDCT). The proposed IP core has been developed based on the design concept of programmable processors to(More)
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. We first use a maximum-weighted independent set formulation for voltage reduction on(More)
This paper presents a discussion of methods to solve multiple way partitioning problems under three different objective functions. A multicommodity flow fzeatmertt is proposed for partitioning without a size wmstrain~ and an iterative improvement algorithm is proposed for partitioning with a size comt.rstint. This algoriti incorporates a top-down clustering(More)
A low-power high-SFDR CMOS direct digital frequency synthesizer (DDFS) is presented. Several design techniques, including a cell-based lookup table, a power aware parameters selection method, a reduced multiplier, a speededup adder/subtracter, an extra pipeline stage, and supply voltage scaling, are used to make the design more easily synthesizable and much(More)