Ching-Hua Hsiao

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This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25μm 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A(More)
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