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In this paper, a low-cost 256-point FFT processor design is presented for portable speech and audio applications. After an intensive review of existing FFT architectures, a single-butterfly FFT architecture is chosen to obtain low cost. In this single-butterfly FFT architecture, a two-multiplier and three-adder pipelined butterfly unit is proposed to(More)
In this paper, we present a novel memory-efficient high-throughput scalable architecture for multi-level 2-D DWT. We studied the existing DWT architectures and observed that data scanning method has a significant impact on the memory efficiency of DWT architecture. We propose a novel parallel stripe-based scanning method based on the analysis of the(More)
In present scenario high speed and low power devices in signal processing system is generally needed the efficient design and reduced complexity of converters, therefore conventional flash ADC is not fully meet the required specifications. ADC with high speed and low resolution is required in present communication technologies. Lower leakage current with(More)
This paper studies the energy consumed in VLSI systems that have multiple-stage functionally pipelined datapath. A two-process approach is then proposed to synthesize such datapath by partitioning the datapath into multiple pipelined stages that can be operated with multiple frequencies and multiple supply voltages, aiming to reduce energy consumed by the(More)
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