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—This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times(More)
—This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscil-lator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD)(More)
—In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with(More)
—A new DLL-based approach for all-digital multi-phase clock generation is presented. By using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be(More)
—This brief presents an autocalibrated all-digital temperature sensor circuit for use with on-chip thermal sensing applications. The proposed temperature sensor eliminates the need for two-temperature-point calibration in prior temperature sensors. Therefore, temperature sensor calibration efforts in high-volume production can be significantly reduced. The(More)
This paper presents a new ADPLL solution for SoC applications. The proposed ADPLL can be implemented with cell library. Including In this paper, we propose a very high-resolution all-digital phase-the DCO and PFD, all designs of ADPLL can be described with HDL locked loop (ADPLL), which is designed with the cell library and language. Because its(More)
—This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfre-quency band is changed, an overlap region between(More)
—In this paper, we propose a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel 2-level flash time-to-digital converter (TDC) to lock in within 2 reference clock cycles. The novel digitally controlled oscillator (DCO) achieves(More)
ѧ An all-digital built-in jitter measurement (BIJM) circuit is presented in this paper. A frequency divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a vernier ring oscillator (VRO) is used as a time-to-digital converter (TDC) to quantize the jitter information into digital codes. The proposed self-referred(More)