Ching-Che Chung

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This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times(More)
This brief presents an autocalibrated all-digital temperature sensor circuit for use with on-chip thermal sensing applications. The proposed temperature sensor eliminates the need for two-temperature-point calibration in prior temperature sensors. Therefore, temperature sensor calibration efforts in high-volume production can be significantly reduced. The(More)
In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone(More)
An all-digital built-in jitter measurement (BIJM) circuit is presented in this paper. A frequency divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a vernier ring oscillator (VRO) is used as a time-to-digital converter (TDC) to quantize the jitter information into digital codes. The proposed self-referred(More)
This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD)(More)
This paper presents an all-digital delay-locked loop (DLL) for DDR SDRAM controller applications. The presented all-digital, cell-based, DLL-based five-phase multi-phase clock generator can generate the required fixed timing delay (tSD) for DDR SDRAM controller to capture the output data (DQ) correctly. The proposed DLL-based multi-phase clock generator(More)
In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for System-OnChip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI(More)
Coded OFDM (COFDM)-based baseband solutions provide up to 480Mb/s data rates for 528MHz ultra wideband (UWB) systems in the 3.1GHz to 10.6GHz RF band [1]. The design challenge for the baseband transceiver is to extend the signal bandwidth to 26.4 times wider than a WLAN system with acceptable design complexity and energy consumption. In this paper, a(More)