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—This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times(More)
—In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with(More)
—This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfre-quency band is changed, an overlap region between(More)
—This brief presents an autocalibrated all-digital temperature sensor circuit for use with on-chip thermal sensing applications. The proposed temperature sensor eliminates the need for two-temperature-point calibration in prior temperature sensors. Therefore, temperature sensor calibration efforts in high-volume production can be significantly reduced. The(More)
—In this paper, we propose a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel 2-level flash time-to-digital converter (TDC) to lock in within 2 reference clock cycles. The novel digitally controlled oscillator (DCO) achieves(More)
—This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the(More)
—A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC). In such applications, the frequency multiplication ratio is always larger than 800 and can be up to over 2600. The output pixel clock has to be phase aligned to the(More)
— A novel fully digital CMOS smart temperature sensor with auto-calibration circuit in 65nm CMOS technology is presented. The proposed auto-calibration circuit can greatly reduce the temperature calibration efforts, and therefore it is very suitable for on-chip dynamic thermal management applications. The power consumption of the proposed circuit is 55μW(More)
—In this paper, a novel portable and all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with low-power consumption is presented. The proposed ADSSCG can provide flexible spreading ratios by the proposed rescheduling division triangular modulation (RDTM). Thus it can provide different EMI attenuation(More)
—In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for System-On-Chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI(More)