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This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided. The(More)
In this paper constructions are given for combining two, three, or four codes to obtain new codes. The AndryanovSaskovets construction is generalized. It is shown that the Preparata double-error-correcting codes may be extended by about (block length) " ' symbols, of which only one is a check symbol, and that e-error-correcting BCH codes may sometimes be(More)