Chin K. Yeong

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In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area­ delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MCF) for 4-level signals is developed. Results show that our(More)
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