Chin Hau Hoo

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Routing of nets is one of the most time consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose a scalable way of parallelizing the routing algorithm through Lagrangian relaxation. The FPGA routing problem is formulated as a linear(More)
Routing of nets is one of the most time-consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose ParaFRo, a two-phase hybrid parallel FPGA router using fine-grained synchronization and partitioning. The first phase of the router(More)
With the increasing number of processors in Multiprocessor System-on-Chips (MPSoCs), Network-on-Chips (NoCs) are replacing conventional buses as the interprocessor communication architecture. Since different use cases might be running on MPSoCs, there is a need for dynamically reconfigurable NoC. However, most dynamically reconfigurable NoCs have a large(More)
Leakage power has become an important component of the total power consumption in FPGAs as process technology shrinks. In addition, a significant amount of leakage power in FPGAs is consumed by the routing resources. Therefore, leakage power reduction in FPGAs should begin with the routing resources. In this paper, we propose a novel directional(More)
High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but sub-optimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-V<sub>t</sub> design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low(More)
The increase in speed and capacity of FPGAs is faster than the development of effective design tools to fully utilize it, and routing of nets remains as one of the most time-consuming stages of the FPGA design flow. While existing works have proposed methods of accelerating routing through parallelization, they are limited by the memory architecture of the(More)
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