Learn More
—This paper describes MATLAB/Simulink implementation of three induction motor tests, namely dc, no-load, and blocked-rotor tests performed to identify equivalent circuit parameters. These simulation models are developed to support and enhance electric machinery education at the undergraduate level. The proposed tests have been successfully integrated into
This paper reports on an FPGA implementation of sparse LU decomposition. The resulting special purpose hardware is geared towards power system problems-load flow computation-which are typically solved iteratively using Newton Raphson. The key step in this process, which takes approximately 85% of the computation time, is the solution of sparse linear(More)
—Datacenters, being major consumers of power, can play an important role in the ef¿cient operation of electrical grids. This paper develops an optimization framework to allow datacenters to operate as controllable load resources within the demand dispatch regime, a demand response (DR) program in which incentives are designed to induce lower electricity use(More)
This paper is concerned with the development of a fast, programmable, and reconfigurable power system emulator using an analog/mixed-signal VLSI microchip. The proposed microchip is capable of emulating behaviors of large power system networks under various conditions with faster than real-time computation time that is independent of the size of the power(More)
The conventional Newton's method (also known as Newton–Raphson method) for the AC power flow problem is preferred in some situations due to its local quadratic convergence. However, its high computation and memory requirements due to the required LU fac-torization of the Jacobian matrix at each iteration limit its practical employment in the online(More)
— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper will review various problems and proposed solutions encountered from the design stage to PC-board hardware implementation to anticipated VLSI implementation. It has already been noted(More)