Chiharo Mizuno

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We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of " clustered Voltage Scaling (CVS) scheme " and " Bow by Row optimized Power &pply (RRPS) scheme ". By the CVS scheme, the(More)
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