Chih-Mou Tseng

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Built-in Self Test (BIST) is a crucial technique for testing embedded memory cores in a System-on-Chip (SoC). However, there is not much published work on BIST design optimization for <i>multiple</i> memory cores in the SoC designs. In this paper, we present a method for the BIST design optimization problem for large-scale SoC embedded memory cores,(More)
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power(More)
This paper presents a design for testability technique to avoid scan shift failure due to flip-flop simultaneous triggering. The proposed technique changes test clock domains of flip-flops in the regions where severe IR-drop problems occur. A massive parallel algorithm using a graphic processor unit is adopted to speed up the IR-drop simulation during(More)
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