Chih-Kong Ken Yang

Learn More
—This paper investigates the effects of varying phase-locked loop (PLL) design parameters on timing jitter. The noise due to voltage-controlled oscillator (VCO), input clock and buffering clock are considered. First, a closed-form equations are derived that relate PLL output clock jitter to parameters of a second-order PLL, i.e., damping factor and(More)
—This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time inter-leaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the(More)
—A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample–hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation.(More)
—We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor–one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the(More)
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to(More)