Chih-Kong Ken Yang

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An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel lowpass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and(More)
This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8 the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8 FO-4)] and 1.5 GHz [=1/(6.7 FO-4)] for two(More)
This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in(More)
gy, coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include(More)
This paper investigates the effects of varying phaselocked loop (PLL) design parameters on timing jitter. The noise due to voltage-controlled oscillator (VCO), input clock and buffering clock are considered. First, a closed-form equations are derived that relate PLL output clock jitter to parameters of a second-order PLL, i.e., damping factor and bandwidth.(More)
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample–hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation.(More)
This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the(More)
Implementing serial I/O receivers based on analog-todigital converters (ADCs) and digital signal post-processing has drawn growing interest with technology scaling, but power consumption remains among the key issues for such digital receiver in high speed applications. This paper presents an ADC-based receiver that uses a low-gain analog and mixed-mode(More)
A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8m CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform(More)