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— A serial link transmitter fabricated in the LSI 0.4-µm CMOS process uses multi-level signaling (4-PAM) and a 3-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock(More)
— A receiver for OC-48 (2.488Gbps) serial data is designed using an 0.8µm CMOS process. Gate speed limitations are overcome using 1:8 demultiplexing at the receiver. To perform clock recovery, data is 3x oversampled. Digital logic processes the oversampled outputs to reconstruct the data bits. A 3x3mm 2 test chip is built. The demand for higher bit rates by(More)
Description: This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit(More)
—An 8-Gb/s 0.3-m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency(More)
—This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time inter-leaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the(More)
— Improving fabrication technology enables not only the scaling of on-chip gate speeds but also the data rate of inter-chip communication interfaces. Simple low latency off-chip interfaces are limited by the maximum clock frequency that can be propagated on-chip. More complex serial links break this barrier, by employing high fan-in multiplexing(More)
—This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8 the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8 FO-4)] and 1.5 GHz [=1/(6.7 FO-4)] for two(More)