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— Improving fabrication technology enables not only the scaling of on-chip gate speeds but also the data rate of inter-chip communication interfaces. Simple low latency off-chip interfaces are limited by the maximum clock frequency that can be propagated on-chip. More complex serial links break this barrier, by employing high fan-in multiplexing(More)
—A serial link transmitter fabricated in a large-scale integrated 0.4-m CMOS process uses multilevel signaling (4-PAM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5 : 1 multiplexer to reduce the(More)
—An 8-Gb/s 0.3-m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency(More)
—This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time inter-leaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the(More)
—This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in(More)
—This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8 the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8 FO-4)] and 1.5 GHz [=1/(6.7 FO-4)] for two(More)
—A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample–hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation.(More)
A 4Gb/s serial link transmitter and receiver fabricated in the MOSIS HPO.6~m CMOS process uses edges tapped from a PLL to multiplex (transmit) and demultiplex (receive) the data. For data recovery the input is sampled at 3x the bit rate and uses a digital phase picking logic that allows very fast tracking of the bit window. With a 3.3V supply, the chip has(More)