Chih-Huei Hou

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A single-channel lb/cycle 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. The operation speed is enhanced by using the loop-unrolled technique in the coarse conversions. Moreover, we propose a timing control scheme which would shorten the critical timing path to alleviate the speed(More)
This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code(More)
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