Chih-Hsing Lin

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In this paper, we propose a switching bilateral filter (SBF) with a texture and noise detector for universal noise removal. Operation was carried out in two stages: detection followed by filtering. For detection, we propose the sorted quadrant median vector (SQMV) scheme, which includes important features such as edge or texture information. This(More)
In this paper, a wide-range DLL-based frequency multiplier with PMOS active load for communication applications is proposed. Adding the PMOS active load in the delay cells has the inductive-peaking effect to increase the operation frequency range. The DLL-based frequency multiplier uses simple exclusive-or (XOR) gates and phase blending technique for the(More)
Serial link interconnection has generated a lot of attention in on-chip bus design due to its advantages over multibit parallel interconnection in terms of crosstalk, skew, and area cost. However, serializing a multi-bit parallel bus tends to increase the bit transition and power dissipation. This paper proposes an embedded transition inversion (ETI) coding(More)
A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s(More)
This paper presents a 10.0~11.5 Gb/s full-rate phase and frequency detector integrated with the clock recovery circuit (CRC) for application in optical receivers. A rotational phase and frequency detector (RPFD) without external reference clock is proposed to train the conventional bang-bang phase detector (BBPD) to capture the clock frequency. The proposed(More)
This paper proposes a structure health monitoring device (HMD) with using three 1-axis accelerometers, microprocessor, analog to digital converter (ADC), and data logger for long span bridge. The proposed monitoring system achieves the features of low cost and data synchronization of three 1-axis accelerometers. Furthermore, we develop a packet acquisition(More)
This work demonstrates a real-time bridge structure health monitoring device (HMD) with using three 1-axis accelerometers, Gateway, and analog to digital converter (ADC). The proposed HMD achieves the features of low cost and data synchronization of three 1-axis accelerometers. Furthermore, we develop a packet acquisition program to receive the data from(More)