Chih-Hong Hwang

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As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal–oxide–semiconductor (CMOS) circuits using a 3-D “atomistic” coupled(More)
Article history: Received 30 November 2009 Received in revised form 21 January 2010 Available online 25 March 2010 0026-2714/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.microrel.2010.01.041 * Corresponding author. Address: Department of El Chiao Tung University, 1001 Ta-Hsueh Road, Hsinc 35712121x52974. E-mail address: ymli@faculty.nctu.edu.tw (Y.(More)
As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal-oxide-semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is(More)
Modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. Unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance is nonlinear and hard to be modeled in current compact models. Therefore, a large-scale statistically(More)
Chih-Hong Hwang, Tien-Yeh Li, Ming-Hung Han, Kuo-Fu Lee, Hui-Wen Cheng, and Yiming Li Institute of Communication Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu City, Hsinchu 300, Taiwan Department of Electrical Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu City, Hsinchu 300, Taiwan National Nano Device(More)
High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The(More)
As the dimension of semiconductor device shrunk into nanoscale, characteristic fluctuation is more pronounced, and become crucial for circuit design. Diverse approaches have been reported to investigate and suppress the random-dopant-induced fluctuations in devices. However, attention is seldom drawn to the existence of high-frequency characteristic(More)
In nanoscale silicon FETs, the lateral asymmetric channel (LAC) devices with higher channel doping concentration near the source-end have shown better control of the short channel effects. However, such asymmetric doping profile may introduce different fluctuations in device characteristics. In this paper, the asymmetric sketch of random dopants(More)
Comparison of two different implantation processing techniques for random dopant (RD)-induced threshold voltage fluctuation (sigmaV(th)) in 15-nm metal-oxide-semiconductor (MOS) devices is reported. Implantations of flash lamp annealing and laser spike annealing are simulated using a kinetic Monte Carlo (KMC) technique. The KMC generated distributions are(More)
In this study, a three-dimensional ''atomistic " coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal–oxide–semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on(More)