Chih-Hong Hwang

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Modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. Unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance is nonlinear and hard to be modeled in current compact models. Therefore, a large-scale statistically(More)
—This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold(More)
In this study, a three-dimensional ''atomistic " coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal–oxide–semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on(More)
In nanoscale silicon FETs, the lateral asymmetric channel (LAC) devices with higher channel doping concentration near the source-end have shown better control of the short channel effects. However, such asymmetric doping profile may introduce different fluctuations in device characteristics. In this paper, the asymmetric sketch of random dopants(More)
— In this paper, a placer based on optimizing the power consumption of clock gating technique for low power designs is presented. First, we construct an optimal gated clock topology based on considering the physical connectivity, and minimizing the total switching activity of the clock network. Then, through a novel measure function, our placer can build a(More)
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