Chien-Ching Lin

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In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access(More)
This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free(More)
Comparative sequence analysis of 16S ribosomal (r)RNAs or DNAs of Bacillus alvei, B. laterosporus, B. macerans, B. macquariensis, B. polymyxa and B. stearothermophilus revealed the phylogenetic diversity of the genus Bacillus. Based on the presently available data set of 16S rRNA sequences from bacilli and relatives at least four major "Bacillus clusters"(More)
In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two(More)
A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE(More)
The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different submatrices defined in IEEE 802.16e and IEEE 802.11n. These proposed(More)
Coded OFDM (COFDM)-based baseband solutions provide up to 480Mb/s data rates for 528MHz ultra wideband (UWB) systems in the 3.1GHz to 10.6GHz RF band [1]. The design challenge for the baseband transceiver is to extend the signal bandwidth to 26.4 times wider than a WLAN system with acceptable design complexity and energy consumption. In this paper, a(More)
The min-sum algorithm is the most common method to simplify the belief-propagation algorithm for decoding low-density parity-check (LDPC) codes. However, there exists a performance gap between the min-sum and belief-propagation algorithms due to nonlinear approximation. In this paper, a self-compensation technique using dynamic normalization is thus(More)
This paper presents a universal architecture for Reed–Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder(More)
This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in(More)