Chia-Yi Lin

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This note is devoted to the problem of synthesizing proportional–integral–derivative (PID) controllers for robust performance for a given single-input–single-output plant in the presence of uncertainty. First, the problem of robust performance design is converted into simultaneous stabilization of a complex polynomial family. An extension of the results on(More)
In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also(More)
With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that(More)
This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supply the test patterns either through the <i>compressed scan chain</i> whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using(More)
In this paper, a low noise and robust test scheme for 3D stacked integrated circuits based on modified standard IEEE 1149.4 has been proposed. Through the modified standard, this novel test scheme can be more robust to fulfill the microsystem integration requirements. This test scheme also makes the analog pins more observable and testable during and after(More)
This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and(More)
Polysilicon nanowire (poly-Si NW) based biosensor is integrated with the wireless acquisition circuits in a standard CMOS SoC for the first time. To improve detection quality, a chopper DDA-based analog front-end with features of low noise, high CMRR, and rail-to-rail input range is implemented. Additional temperature sensor is also included to compensate(More)
This study proposes a vascular endothelial growth factor (VEGF) biosensor for diagnosing various stages of cervical carcinoma. In addition, VEGF concentrations at various stages of cancer therapy are determined and compared to data obtained by computed tomography (CT) and cancer antigen 125 (CA-125). The increase in VEGF concentrations during operations(More)
This paper presents a performance based comparative study of various fuzzy logic controllers (FLCs) to control the speed of squirrel-cage induction motor (SCIM) by replacing the conventional proportional??integral (PI) controller. The fuzzy logic based controller does not require any identification of motor dynamic to control its speed and also assures the(More)
The classic dynamic programming approach is not applicable to the airline network revenue management (RM) problem of a practical size due to the curse of dimensionality. Many heuristic methods, including the most popular bid-price control approach, generate the approximate control decisions based on various static formulations, which need to be re-solved to(More)