Chia-Hsien Liu

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This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has <i>distributed and ping-pong register organization</i> optimized for stream processing. To minimize hardware, the DSP mode has no control construct for(More)
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