ChiCheong Shen

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Based on our recent investigation on HfO/sub 2/ high-k gate dielectrics, we review the Hf based gate dielectric in the future ULSI CMOS devices in the following aspects: How long HfO/sub 2/ can be used satisfactorily, assessed from the gate tunneling and scalability; how thin EOT can be grown technologically assessed by interfacial layer thickness; and how(More)
A new planar split dual gate (PSDG) MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device(More)
Bulk Schottky silicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0 /spl sim/ 2.5nm HfO/sub 2/ gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi silicide show excellent electrical performance of I/sub on//I/sub off//spl sim/ 10/sup 7/ - 10/sup 8/ and subthreshold slop(More)
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