Chi-Wook Kim

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A 1.2 V 4 Gb DDR4 SDRAM is presented in a 30 nm CMOS technology. DDR4 SDRAM is developed to raise memory bandwidth with lower power consumption compared with DDR3 SDRAM. Various functions and circuit techniques are newly adopted to reduce power consumption and secure stable transaction. First, dual error detection scheme is proposed to guarantee the(More)
For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing(More)
A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using 1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, 2) a delay-locked-loop circuit using a high-speed and small-swing differential(More)
This paper describes DLL architecture and ZQ calibration method for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM. Proposed DLL consists of one DLL with CML DCDL and another DLL with CMOS DCDL which tracks first one for low jitter and low power characteristics. Quantization error minimized (QEM) ZQ calibration is proposed for better signal integrity and yield(More)
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