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This paper presents a static timing analyzer for flexible TFT circuits (STAF). Gate delay models are first characterized by SPICE simulation as a function of load capacitance and mobility. A block-based STA algorithm is then applied to identify the longest path delay and shortest path delay change in different regions under bending. STAF plots maps that(More)
This paper compares very-low-voltage (VLV) testing and quiescent power supply current (I<sub>DDQ</sub>) testing for amorphous silicon thin-film transistor (a-Si TFT) NMOS digital circuits. As many as 140 circuits-under-test (CUT) of two different design styles are implemented in 8 &#x03BC;m a-Si TFT technology on the glass substrate. All CUT are tested both(More)
Sparsity is a brain-inspired property that enables a significant reduction in workload and power dissipation of deep learning. This work presents a 1.40mm<sup>2</sup> 40nm CMOS sparse neuromorphic processor that implements a two-layer convolutional restricted Boltzmann machine (CRBM) for inference and a support vector machine (SVM) classifier. The processor(More)
  • Chester Liu
  • 2013 International Conference on Field…
  • 2013
This paper presents a highly scalable hardware solver for Blokus Duo. Based on flat Monte Carlo method, the proposed solver contains self-contained agents whose number is configurable and only limited by FPGA capacity, which makes the proposed solver highly scalable. Data structures and tile representations are tailored to support efficient memory usage and(More)
A configurable neuro-inspired inference processor is designed as an array of neurons each operating in an independent clock domain. The processor implements a recurrent network using efficient sparse convolutions with zero-patch skipping for feedforward operations, and sparse spike-driven reconstruction for feedback operations. A globally asynchronous(More)
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