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  • Chenjie Gu
  • IEEE Transactions on Computer-Aided Design of…
  • 2011
We present a projection-based nonlinear model order reduction method, named model order reduction via quadratic-linear systems (QLMOR). QLMOR employs two novel ideas: 1) we show that nonlinear ordinary differential equations, and more generally differential-algebraic equations (DAEs) with many commonly encountered nonlinear kernels can be rewritten(More)
Previous model order reduction methods fit into the framework of identifying the low-order linear subspace and using the linear projection to project the full state space into the low-order subspace. Despite its simplicity, the macromodel might automatically include redundancies. In this paper, we present a model order reduction approach, named(More)
Failures and yield problems due to parameter variations have become a significant issue for sub-90-nm technologies. As a result, CAD algorithms and tools that provide designers the ability to estimate the effects of variability quickly and accurately are being urgently sought. The need for such tools is particularly acute for static RAM (SRAM) cells and(More)
In this paper, we describe a novel statistical framework, referred to as <i>Bayesian Model Fusion</i> (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (AMS) circuits with consideration of large-scale process variations. The BMF technique is motivated(More)
Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level(More)
Abstraction of circuits is desirable for faster simulation and high-level system verification. In this paper, we present an algorithm that derives a Mealy machine from differential equations of a circuit by learning input-output trajectories. The key idea is adapted from Angluin's DFA (deterministic finite automata) learning algorithm [1] that learns a DFA(More)
There are increasingly number of analog/mixed-signal circuits in microprocessors and SOCs. A significant portion of mixed-signal circuits are high-speed I/O links, including serial buses such as PCIE and parallel buses such as DDR. Post-silicon validation of I/O links is hard and time-consuming, and can be critical for making a product release qualification(More)
Efficient high-dimensional performance modeling of today's complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from(More)