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Multiprocessor system-on-chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The complexity of MPSoC makes it expensive and time consuming to fully analyze and test during the design stage. This has given rise to the(More)
Hybrid cache architectures have been proposed to mitigate the increasing on-chip power dissipation through the exploitation of the emerging non-volatile memories (NVMs). To overcome the high energy and long latency associated with write operations of NVMs, a small SRAM is typically incorporated into the hybrid cache for accommodating write-intensive cache(More)
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Because of real-time constraints, applications are usually statically parallelized and scheduled onto the target MPSoC so as to obtain predictable worst-case performance. However, both technology scaling(More)
Given its low power consumption and high density, Phase Change Memory (PCM) has been treated as a promising alternative to DRAM for main memory storage. Multilevel Cell (MLC) PCM outperforms regular single level cell (SLC) PCM with even higher information density, yet requires more accurate control for cell reading and writing. More crucially, the(More)
NAND flash memory has been widely adopted in embedded systems as secondary storage. Yet the further development of flash memory strongly hinges on the tackling of its inherent implausible characteristics, including read and write speed asymmetry, inability of in-place update, and performance harmful erase operations. While Write Buffer Cache (WBC) has been(More)
Due to its low power consumption and high density, phase change memory (PCM) becomes a promising main-memory alternative to DRAM in embedded systems. PCM, however, has the endurance problem in which the number of rewrites to each cell is quite limited compared with DRAM. Therefore, it is fundamental to eliminate unnecessary writes in PCM-based embedded(More)
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic branch prediction subsystems to hide the execution latency of control-altering instructions. In this paper a low power early branch identification technique which enables the design(More)
The computing engines of many current applications are powered by MPSoC platforms, which promise significant speedup but induce increased reliability problems as a result of ever growing integration density and chip size. While static MPSoC execution schedules deliver predictable worst-case performance, the absence of dynamic variability unfortunately(More)
Improving the endurance of Phase change memory (PCM) is a fundamental issue when the technology is considered as an alternative to main memory usage. Existing wear-leveling techniques overcome this challenge through constantly remapping hot virtual pages, engendering a fair amount of extra write operations to PCM and imposing considerable energy overhead.(More)