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Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
TLDR
This paper has proposed an algorithm for flip-flop replacement for power reduction in digital integrated circuit design. Expand
  • 62
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Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits
TLDR
We propose a simulated annealing based approach to construct a common-centroid placement which exhibits the highest possible degree of dispersion to reduce the random mismatch. Expand
  • 27
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Routability-driven placement algorithm for analog integrated circuits
TLDR
We present a two-stage routability-driven analog placer based on ASF-B*tree and HB*-tree representations that can effectively minimize routing congestion without violating the symmetry property after placement expansion. Expand
  • 15
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Performance-driven analog placement considering boundary constraint
TLDR
We introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands to meet the boundary property of ASF-B∗ tree. Expand
  • 19
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A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme
TLDR
In high-speed Flash analog-to-digital converters, preamplifiers are often placed in front of a comparator to reduce metastability errors and enhance comparison speed. Expand
  • 47
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Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors
TLDR
A simulated-annealing-based approach for mismatch-aware common-centroid placement with the highest possible degree of dispersion for an arbitrary-ratio capacitor array under the consideration of systematic and random mismatches. Expand
  • 29
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A bias-driven approach for automated design of operational amplifiers
TLDR
This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). Expand
  • 26
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Routing-aware placement algorithms for modern analog integrated circuits
TLDR
In this paper, some issues about placement and routing for analog circuits are discussed, which include prevention of noisy signals in symmetry islands, congestion elimination in practical placement, and routing area reduction in capacitor arrays. Expand
  • 7
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Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits
TLDR
We explore the attributes of a good capacitor placement, which can reduce gradient errors and increase capacitance correlation. Expand
  • 8
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A 2-GS/s 6-bit flash ADC with offset calibration
TLDR
A 6-bit flash analog-to-digital converter with a digital offset calibration scheme is fabricated in a 0.13-mum CMOS process. Expand
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