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  • Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh
  • Engineering
  • International Symposium on Integrated Circuits
  • 2011 (First Publication: 1 December 2011)
  • This paper presents an all digital delay-locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, andContinue Reading
  • Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu
  • Computer Science
  • Symposium on VLSI Circuits (VLSIC)
  • 2012 (First Publication: 1 June 2012)
  • This paper describes the design of a multi-GHz ADDLL. HDSC-based coarse-fine architecture is adopted to achieve low power and to avoid harmonic locking at large operating frequency ranges. A newContinue Reading