Chen-Yong Cher

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Chip-level power and thermal implications will continue to rule as one of the primary design constraints and performance limiters. The gap between average and peak power actually widens with increased levels of core integration. As such, if per-core control of power levels (modes) is possible, a global power manager should be able to dynamically set the(More)
Although modern superscalar processors achieve high branch prediction accuracy, certain branches either are inherently difficult to predict or incur destructive interference in prediction tables, causing significant performance loss due to mispredictions. We propose a novel microarchitecture, called Skipper, to handle such difficult branches by exploiting(More)
Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot(More)
Choosing the correct error injection technique is of primary importance in simulation-based design and evaluation of robust systems that are resilient to soft errors. Many low-level (e.g., flip-flop-level) error injection techniques are generally used for small systems due to long execution times and significant memory requirements. High-level error(More)
Energy-efficient processor design is becoming moreand more important with technology scaling and with highperformance requirements. Supply-voltage scaling is anefficient way to reduce energy by lowering the operatingvoltage and the clock frequency of processorsimultaneously. We propose a variable supply-voltagescaling (VSV) technique based on the following(More)
Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded dual-core chip. In each SMT core, the IBM POWER5 features two levels of thread resource balancing and prioritization. The first level(More)
Controlling power consumption and temperature is of major concern for modern computing systems. In this work we characterize thermal behavior and power consumption of an IBM POWER6-based system. We perform the characterization at several levels: application, operating system, and hardware level, both when the system is idle, and under load. At hardware(More)
A processing-in-memory architecture for exascale systems R. Nair S. F. Antao C. Bertolli P. Bose J. R. Brunheroto T. Chen C.-Y. Cher C. H. A. Costa J. Doi C. Evangelinos B. M. Fleischer T. W. Fox D. S. Gallo L. Grinberg J. A. Gunnels A. C. Jacob P. Jacob H. M. Jacobson T. Karkhanis C. Kim J. H. Moreno J. K. O’Brien M. Ohmacht Y. Park D. A. Prener B. S.(More)
Full-chip thermal monitoring is an important and challenging issue in today's microprocessor design. In this paper, we propose a new information-theoretic framework to quantitatively model the uncertainty of on-chip temperature variation by differential entropy. Based on this framework, an efficient optimization scheme is developed to find the optimal(More)