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Motion compensation is always the main bottleneck in real-time or high quality video applications; thus, fast and efficient motion compensation is necessary. In this paper, a new motion compensation design is presented to overcome large calculation time of complicated motion vector prediction (MVP) algorithm and high motion resolution in H.264/AVC. By(More)
An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based(More)
This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times(More)
In this brief, a generalized mixed-radix (GMR) algorithm is proposed for memory-based fast Fourier transform (FFT) processors to support prime-sized and traditional 2 -point FFTs simultaneously. It transforms the index to a multidimensional vector for efficient computation. By controlling the index vector to satisfy the “vector reverse” behavior, the GMR(More)
In this paper, a Reed–Solomon Product-Code (RS-PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp–Massey algorithm. The proposed(More)
In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to(More)
In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access(More)